), the first latch (Master) is transparent, sampling the input data When the clock transitions to high (
CMOS logic levels are close to the supply rails ( VDDcap V sub cap D cap D end-sub GNDcap G cap N cap D Flip Flop Circuit Using Cmos
), the Master latch locks the data, and the second latch (Slave) becomes transparent, passing the stored value to the output ), the first latch (Master) is transparent, sampling